cpu.c
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1 /*
2  * CPU detection code, extracted from mmx.h
3  * (c)1997-99 by H. Dietz and R. Fisher
4  * Converted to C and improved by Fabrice Bellard.
5  *
6  * This file is part of Libav.
7  *
8  * Libav is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU Lesser General Public
10  * License as published by the Free Software Foundation; either
11  * version 2.1 of the License, or (at your option) any later version.
12  *
13  * Libav is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16  * Lesser General Public License for more details.
17  *
18  * You should have received a copy of the GNU Lesser General Public
19  * License along with Libav; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21  */
22 
23 #include <stdlib.h>
24 #include <string.h>
25 #include "libavutil/x86_cpu.h"
26 #include "libavutil/cpu.h"
27 
28 /* ebx saving is necessary for PIC. gcc seems unable to see it alone */
29 #define cpuid(index,eax,ebx,ecx,edx)\
30  __asm__ volatile\
31  ("mov %%"REG_b", %%"REG_S"\n\t"\
32  "cpuid\n\t"\
33  "xchg %%"REG_b", %%"REG_S\
34  : "=a" (eax), "=S" (ebx),\
35  "=c" (ecx), "=d" (edx)\
36  : "0" (index));
37 
38 #define xgetbv(index,eax,edx) \
39  __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
40 
41 /* Function to test if multimedia instructions are supported... */
43 {
44  int rval = 0;
45  int eax, ebx, ecx, edx;
46  int max_std_level, max_ext_level, std_caps=0, ext_caps=0;
47  int family=0, model=0;
48  union { int i[3]; char c[12]; } vendor;
49 
50 #if ARCH_X86_32
51  x86_reg a, c;
52  __asm__ volatile (
53  /* See if CPUID instruction is supported ... */
54  /* ... Get copies of EFLAGS into eax and ecx */
55  "pushfl\n\t"
56  "pop %0\n\t"
57  "mov %0, %1\n\t"
58 
59  /* ... Toggle the ID bit in one copy and store */
60  /* to the EFLAGS reg */
61  "xor $0x200000, %0\n\t"
62  "push %0\n\t"
63  "popfl\n\t"
64 
65  /* ... Get the (hopefully modified) EFLAGS */
66  "pushfl\n\t"
67  "pop %0\n\t"
68  : "=a" (a), "=c" (c)
69  :
70  : "cc"
71  );
72 
73  if (a == c)
74  return 0; /* CPUID not supported */
75 #endif
76 
77  cpuid(0, max_std_level, ebx, ecx, edx);
78  vendor.i[0] = ebx;
79  vendor.i[1] = edx;
80  vendor.i[2] = ecx;
81 
82  if(max_std_level >= 1){
83  cpuid(1, eax, ebx, ecx, std_caps);
84  family = ((eax>>8)&0xf) + ((eax>>20)&0xff);
85  model = ((eax>>4)&0xf) + ((eax>>12)&0xf0);
86  if (std_caps & (1<<23))
87  rval |= AV_CPU_FLAG_MMX;
88  if (std_caps & (1<<25))
89  rval |= AV_CPU_FLAG_MMX2
90 #if HAVE_SSE
92  if (std_caps & (1<<26))
93  rval |= AV_CPU_FLAG_SSE2;
94  if (ecx & 1)
95  rval |= AV_CPU_FLAG_SSE3;
96  if (ecx & 0x00000200 )
97  rval |= AV_CPU_FLAG_SSSE3;
98  if (ecx & 0x00080000 )
99  rval |= AV_CPU_FLAG_SSE4;
100  if (ecx & 0x00100000 )
101  rval |= AV_CPU_FLAG_SSE42;
102 #if HAVE_AVX
103  /* Check OXSAVE and AVX bits */
104  if ((ecx & 0x18000000) == 0x18000000) {
105  /* Check for OS support */
106  xgetbv(0, eax, edx);
107  if ((eax & 0x6) == 0x6)
108  rval |= AV_CPU_FLAG_AVX;
109  }
110 #endif
111 #endif
112  ;
113  }
114 
115  cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
116 
117  if(max_ext_level >= 0x80000001){
118  cpuid(0x80000001, eax, ebx, ecx, ext_caps);
119  if (ext_caps & (1U<<31))
120  rval |= AV_CPU_FLAG_3DNOW;
121  if (ext_caps & (1<<30))
122  rval |= AV_CPU_FLAG_3DNOWEXT;
123  if (ext_caps & (1<<23))
124  rval |= AV_CPU_FLAG_MMX;
125  if (ext_caps & (1<<22))
126  rval |= AV_CPU_FLAG_MMX2;
127 
128  /* Allow for selectively disabling SSE2 functions on AMD processors
129  with SSE2 support but not SSE4a. This includes Athlon64, some
130  Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster
131  than SSE2 often enough to utilize this special-case flag.
132  AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case
133  so that SSE2 is used unless explicitly disabled by checking
134  AV_CPU_FLAG_SSE2SLOW. */
135  if (!strncmp(vendor.c, "AuthenticAMD", 12) &&
136  rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) {
137  rval |= AV_CPU_FLAG_SSE2SLOW;
138  }
139 
140  /* XOP and FMA4 use the AVX instruction coding scheme, so they can't be
141  * used unless the OS has AVX support. */
142  if (rval & AV_CPU_FLAG_AVX) {
143  if (ecx & 0x00000800)
144  rval |= AV_CPU_FLAG_XOP;
145  if (ecx & 0x00010000)
146  rval |= AV_CPU_FLAG_FMA4;
147  }
148  }
149 
150  if (!strncmp(vendor.c, "GenuineIntel", 12)) {
151  if (family == 6 && (model == 9 || model == 13 || model == 14)) {
152  /* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")
153  * theoretically support sse2, but it's usually slower than mmx,
154  * so let's just pretend they don't. AV_CPU_FLAG_SSE2 is disabled and
155  * AV_CPU_FLAG_SSE2SLOW is enabled so that SSE2 is not used unless
156  * explicitly enabled by checking AV_CPU_FLAG_SSE2SLOW. The same
157  * situation applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
160  }
161  /* The Atom processor has SSSE3 support, which is useful in many cases,
162  * but sometimes the SSSE3 version is slower than the SSE2 equivalent
163  * on the Atom, but is generally faster on other processors supporting
164  * SSSE3. This flag allows for selectively disabling certain SSSE3
165  * functions on the Atom. */
166  if (family == 6 && model == 28)
167  rval |= AV_CPU_FLAG_ATOM;
168  }
169 
170  return rval;
171 }