Optimizations for VLIW/EPIC Architectures
Overview
Many newer architectures such as the upcoming IA-64 and the
DSPs such as the C6 are VLIW or so called EPIC machines.
These architectures depends on the compiler to
extract instruction level parallelism (ILP)
and data level parallelism (DLP).
Optimizations for these architectures include:
- Hyperblock construction
- Predication and predicate analysis
- Hyperblock scheduling
- Modulo scheduling
Hyperblocks
Predicate Analysis
Hyperblock Scheduling
Modulo Scheduling
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Last modified: Mon Jun 8 14:18:05 UTC 2009 by buildd@vernadsky
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