List of all members.
Public Member Functions |
virtual void | reset (void) |
uint8_t | read (uint_least8_t addr) |
void | write (uint_least8_t addr, uint8_t data) |
const char * | credits (void) |
void | clock (float64_t clock) |
virtual const char * | error (void)=0 |
Friends |
class | TimerA |
class | TimerB |
Constructor & Destructor Documentation
Create a new CIA.
- Parameters:
-
Member Function Documentation
void MOS6526::bTick |
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void |
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protected |
This event exists solely to break the ambiguity of what scheduling on top of PHI1 causes, because there is no ordering between events on same phase. Thus it is scheduled in PHI2 to ensure the b.event() is run once before the value changes.
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PHI1 a.event() (which calls underFlow())
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PHI1 b.event()
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PHI2 bTick.event()
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PHI1 a.event()
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PHI1 b.event()
void MOS6526::clear |
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void |
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protected |
void MOS6526::clock |
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float64_t |
clock | ) |
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Set day-of-time event occurence of rate.
- Parameters:
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const char* MOS6526::credits |
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void |
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inlinevirtual |
Get the credits.
- Returns:
- the credits
Implements component.
virtual void MOS6526::interrupt |
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bool |
state | ) |
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protectedpure virtual |
uint8_t MOS6526::read |
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uint_least8_t |
addr | ) |
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virtual |
Read CIA register.
- Parameters:
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addr | register address to read (lowest 4 bits) |
Implements component.
void MOS6526::reset |
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void |
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virtual |
void MOS6526::serialPort |
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protected |
void MOS6526::tod |
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void |
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protected |
void MOS6526::trigger |
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void |
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protected |
void MOS6526::trigger |
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const uint8_t |
interruptMask | ) |
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protected |
Trigger an interrupt.
- Parameters:
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interruptMask | Interrupt flag number |
void MOS6526::underflowA |
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void |
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protected |
void MOS6526::underflowB |
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void |
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protected |
void MOS6526::write |
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uint_least8_t |
addr, |
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uint8_t |
data |
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) |
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virtual |
Write CIA register.
- Parameters:
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addr | register address to write (lowest 4 bits) |
data | value to write |
Implements component.
Member Data Documentation
Interrupt control register
uint8_t MOS6526::regs[0x10] |
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protected |
These are all CIA registers.
bool MOS6526::triggerScheduled |
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protected |
Have we already scheduled CIA->CPU interrupt transition?
The documentation for this class was generated from the following files: